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Design and Implementation of an All Digital Phase Locked Loop using a Pulse Output Direct Digital Frequency Synthesizer
| Content Provider | Semantic Scholar |
|---|---|
| Author | Gothandaraman, Akila |
| Copyright Year | 2004 |
| Abstract | Phase Locked Loops (PLLs) are widely used in clock recovery and frequency synthesis. Fu l ly Digital PLLs are more suitable for the monol ith ic implementation with other circu its compared to the traditional implementations of the PLLs. The All Digital PLLs are also independent of process variations and can be easi ly ported to different technologies. This thesis presents the design of an Al l Digital Phase Locked Loop (ADPLL) using a pu lse output Direct Digital Frequency Synthesizer (DDFS) and an Al l Digital Phase Frequency Detector (ADPFD) . General design criteria are summarized for the all d igital implementation in comparison to the trad itional approaches and analog implementations. The design has been fabricated using 0 .6-)J.m CMOS technology. The ADPLL has 1 6-bit b inary control and can operate in the frequency range between 1 MHz and 500 MHz. The ADPLL has 50-cycles lock time and a duty cycle distortion of less than 2% . The simulation and test results of the ADPLL are also presented to verify its operation . |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://trace.tennessee.edu/cgi/viewcontent.cgi?article=4030&context=utk_gradthes |
| Alternate Webpage(s) | https://trace.tennessee.edu/cgi/viewcontent.cgi?article=4030&context=utk_gradthes&httpsredir=1&referer= |
| Alternate Webpage(s) | http://trace.tennessee.edu/cgi/viewcontent.cgi?article=4030&context=utk_gradthes |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
