Loading...
Please wait, while we are loading the content...
Similar Documents
Processing In Memory: Chips to Petaflops
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kogge, Peter M. Brockman, Jay B. Sterling, Thomas L. Gao, Guang R. |
| Copyright Year | 1997 |
| Abstract | This paper discusses the potential use of Processing-InMemory (PIM) Technology in petaflops level computing. It starts with a quick review of a proposed PIM architecture called Shamrock, and follows that up with a discussion of several execution models that the architecture supports. Sizings for a petaflops-level machine constructed solely from PIM devices at several points in time are given. This is then projected to how PIM architectures will play a pivotal role in the recently initiated HTMT (Hybrid Technology MultiThreaded) petaflops system architecture project. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://iram.cs.berkeley.edu/isca97-workshop/w2-110.ps |
| Alternate Webpage(s) | http://www.cs.ucf.edu/courses/cda5106/summer02/papers/kogge97PIM.pdf |
| Journal | ISCA 1997 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |