NDLI: PIM architectures to support petaflops level computation in the HTMT machine

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PIM architectures to support petaflops level computation in the HTMT machine

Content Provider	IEEE Xplore Digital Library
Author	Kogge, P.M. Brockman, J.b. Freeh, V.W.
Copyright Year	2000
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA (Kogge, P.M.)
Abstract	The HTMT project is an ambitions attempt to combine a variety of emerging technologies into a petaflops-level computing system available many years before an equivalent machine can be built from current technologies. One of the key problems in such an architecture is overcoming latencies between the main memory and the high performance CPUs, which can grow to literally tens of thousands of cycles. In HTMT the approach taken to overcoming this is a multi-level memory system, with most of the levels to be fabricated using Processing-In-Memory (PIM) technologies in architectures which actively manage the flow of data without centralized CPU control. This paper overviews the current architecture for such chips within the context of the HTMT system, and how this architecture supports the expected execution model.
Starting Page	35
Ending Page	44
File Size	968672
Page Count	10
File Format	PDF
ISBN	076950650X
DOI	10.1109/IWIA.1999.898841
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Delay Memory management Risk management Parallel processing Centralized control Control systems Context modeling Supercomputers Energy management
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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