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A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling
| Content Provider | Semantic Scholar |
|---|---|
| Author | Guo, Jyh-Chyurn |
| Copyright Year | 2006 |
| Abstract | A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 nm. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NF/sub min/ (minimum noise figure), R/sub n/ (noise resistance), Re(Y/sub sopt/), and Im(Y/sub sopt/) for the sub-100-nm RF nMOS devices. The intrinsic NF/sub min/ extracted by the new de-embedding method reveal that NF/sub min/ at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f/sub T/ to 100-GHz level and the effectively reduced gate resistance by multifinger structure. |
| Starting Page | 339 |
| Ending Page | 347 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/ted.2005.862699 |
| Alternate Webpage(s) | https://ir.nctu.edu.tw/bitstream/11536/12652/1/000234850600021.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/ted.2005.862699 |
| Volume Number | 53 |
| Journal | IEEE Transactions on Electron Devices |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
