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A Low-Cost High-Speed Pulse Response Based Built-In Self Test For Analog Integrated Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | San-Um, Wimol Masayoshi, Tachibana Non-Members |
| Copyright Year | 2009 |
| Abstract | This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable delay line for generating pulse stimuli, and a sample-andhold circuit with comparators for fault detection process. Demonstrations of the testing for a Sallen-Key low-pass fllter using 0.18-?m CMOS technology yields relatively high fault coverage. The fault coverage of catastrophic faults is 100%, and the fault coverage of capacitor and resistor variations are 93.75% and 87.5%, respectively. The proposed BIST technique uses low testing time within two short pulse response waveforms, and ofiers low implementation cost since on-chip sinusoidal stimuli, test algorithms, and external digital processing unit are not necessary. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ecti-thailand.org/assets/papers/946_pub_29.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
