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A full-pipelined 2-D IDCT / IDST VLSI architecture with adaptive block-size for HEVC standard
| Content Provider | Semantic Scholar |
|---|---|
| Author | Edirisuriya Madanayake Cintra Bayer |
| Copyright Year | 2013 |
| Abstract | High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4×4 to 32×32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65 nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480MHz and the hardware cost is about 115.8K Gates. Experimental results show that the proposed architecture is able to deal with realtime HEVC IDCT/IDST of 4K×2K (4096×2048)@30 fps video sequence at 171MHz in average. In consequence, it offers a costeffective solution for the future UHDTV applications. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.jstage.jst.go.jp/article/elex/10/9/10_10.20130210/_pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
