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Low Power Functional Verification and Closure of Power Intent Cadence Design Systems
| Content Provider | Semantic Scholar |
|---|---|
| Author | Canvas, Neyaz Khan |
| Copyright Year | 2007 |
| Abstract | As gate densities increase with the availability of newer deep-submicron processes, and as designers cram more functionality on a typical SoC, the limiting factor has very quickly become the power dissipation on a chip. Functional verification which was already a major bottleneck in today’s fast paced electronics industry, is becoming an increasingly more difficult problem as designers implement advanced power management techniques on a chip. There is an urgent need to include power verification as part of the RTL verification process. This paper focuses on the verification of power intent which has traditionally been ignored during the RTL development process. It examines the available power management techniques and also proposes a way to include power verification as part of a comprehensive verification plan. It concludes with an example of verification automation for functional closure of power intent. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.cadence.com/rl/Resources/conference_papers/111Paper.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
