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Efficient and Exhaustive Floating Point Verification Using Sequential Equivalence Checking
| Content Provider | Semantic Scholar |
|---|---|
| Author | Pouarz, Travis W. |
| Copyright Year | 2016 |
| Abstract | Sequential Equivalence Checking is the process of proving formal equivalence between two non-state matching implementations of a given design specification. Nowhere has the VLSI industry adopted this technology as much as to prove correctness of floating point designs against a given reference model. Any error in floating point operations can have severe consequences. ARM and Mentor have partnered to undertake the formal verification of some of the most difficult floating point blocks, including FMUL, FMA, FDIV, and FSQRT, in their CPU designs. We also worked outside the FPU, on a Branch Predictor from the same CPU designs. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://s3.amazonaws.com/verificationacademy-news/DVCon2017/Papers/dvcon-2017_efficient-and-exhaustive-floating-point-verification-using-sequential-equivalence-checking_paper.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
