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High Inversion Current in Silicon Nanowire Field Effect Transistors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Koo, Sang-Mo Fujiwara, Akira Han, Jin-Ping Vogel, Eric M. Richter, C. A. Bonevich, John E. |
| Abstract | Silicon nanowire (SiNW) field effect transistors (FETs) with channel widths down to 20 nm have been fabricated by a conventional “top-down” approach by using electron-beam lithography. The SiNW device shows higher inversion channel current density than the control devices. The extracted electron inversion mobility of the 20 nm width nanowire channel ( ≈1000 cm2/Vs) is found to be 2 times higher than that of the reference MOSFET ( ≈480 cm2/Vs) of large dimension ( W g 1 μm). We attribute this mobility increase to strain-induced changes in the band structure of the SiNW after oxidation. Recently, semiconductor nanowire (NW) field-effect transistors (FETs) have drawn considerable attention as building blocks for highly downscaled electronic devices with superior performance. FETs have been formed from various semiconducting NWs by both “bottom-up” (assembly) and “topdown” (lithography) approaches. For the case of the bottomup approach, extensive effort has been devoted to singlewalled carbon nanotube FETs 1 and silicon nanowire (SiNW) FETs,2 which have shown transistor performance exceeding that of FETs fabricated in single-crystalline bulk silicon. For example, carrier mobility values of 20 000 cm 2/Vs and 1350 cm2/Vs at room temperature have been reported for singlewalled carbon nanotubes 1 and silicon SiNWs 2, respectively. In particular, the performance of SiNW FETs is potentially important for mainstream silicon technology as device dimensions approach 10 nm. However, most of the reported mobility values are not for an inversion channel but are bulk channel values in depletion-mode NW FETs. Furthermore, ohmic contact formation is hard to attain in NW structures, and the inversion layer mobility of SiNW still remains poorly understood. To investigate the transport properties of the inversion channel of SiNWs, it is highly desirable to measure NW FETs with n-p-n doping and good ohmic contacts. 3,4 In this work, the inversion channel transport properties of SiNW FETs made by using conventional semiconductor fabrication techniques have been systematically studied and compared to those of reference metal-oxide-semiconductor (MOS) FET channels. The results show that the inversion channel mobility of SiNWs is 1.3 to 2.2 times higher than that extracted from larger dimension reference devices. The devices used in this study are n-channel SiNW FETs fabricated from a p-type silicon-on-insulator (SOI) wafer with n+ source and drain. Figure 1 shows a schematic top-view of a SiNW FET, which has a [110]-oriented channel on (001) wafer. The FETs have been fabricated by the conventional MOSFET process, where the thickness of the SiNW can be controlled to the nanometer scale. 5,6 The NW channels have been defined by electron beam lithography, and phosphorusdoped polycrystalline Si has been used as the top gate. Al has been used as metal electrodes for the source, drain, gate, and backside gate contacts. To determine the exact dimensions of the nanowire channels, cross-sectional transmission electron microscopy (TEM) has been used. Figure 1C shows a TEM image of the cross section of the SiNW channel along the line B-B′. The SiNW channel is thinner ( WS4 ≈ 12 nm) than the center of the SOI bulk channel layer region ( WS1,2,3 ≈ 28 nm) because of the enhancement of oxidation near the pattern edge. 5 The gate oxide over the Si wire is approximately 40 nm thick. Figure 2A-D shows the top-view layout of the fabricated FETs with different channel geometries, and the cross-sectional view of the channel region is shown in Figure 2E. The channel widthW4 of the SiNW is 20 or 34 nm, and * Corresponding author. Tel: (301)-975-8755. Fax: (301)-975-5668. E-mail: smkoo@nist.gov. † NIST Semiconductor Electronics Division. ‡ NTT Basic Research Lab. § NIST Metallurgy Division. NANO LETTERS 2004 Vol. 4, No. 11 2197-2201 10.1021/nl0486517 CCC: $27.50 © 2004 American Chemical Society Published on Web 09/30/2004 the lengthL4 is 100 nm. 7 SOI channels with various widths (W3 ) 100, 200, and 400 nm) are serially connected to the SiNW channel. All the devices studied in this work are basically SOI FETs with different channel geometries (see Table 1). Figure 3 shows the measured drain current ID as a function of gate voltageVG for a SiNW FET and reference FETs at a drain voltageVD of 50 mV at room temperature. From these curves the extracted subthreshold slopes S ) dVG/ d(log(ID)) were about 65 mV/dec, indicating good interface properties between the oxide and Si substrate. 8 A negative back gate biasVBG efficiently changesVth for all the devices to the positive direction, and the double hump behavior is due to the difference inVth in the edge parts of the 30 μm wide channel. On the other hand, for positive VBG, the negative shift inVth of the NW channel is less compared to that of the reference FETs. Since the top gate covers the SiNW not only from the top surfaces but also from the both sidewalls of the channel, the VBG has less effect on the SiNW devices than on the control devices. For analyzing the mobility, VBG was chosen to b e 0 V in order to have the same threshold voltage for both the NW channels and the |
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| Alternate Webpage(s) | https://ws680.nist.gov/publication/get_pdf.cfm?pub_id=31760 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
