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FPGA implementation of an efficient high-speed DVB-S2X block-interleaver
| Content Provider | Semantic Scholar |
|---|---|
| Author | Vassiliev, Youri Vladimirovitch |
| Copyright Year | 2018 |
| Abstract | An overview of the DVB-S2 modem is given with the focus on the forward error correction block. The block-interleaver in the DVB-S2 and DVB-S2X standard is examined. Different interleaver configurations are evaluated. A suitable way to preform the interleaving process with one block of memory is found. The concept is proven with MATLAB models and implemented in VHDL. The entity has been verified and exceeds the desired performance. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://brage.bibsys.no/xmlui/bitstream/handle/11250/2562787/20080_FULLTEXT.pdf?isAllowed=y&sequence=1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |