Loading...
Please wait, while we are loading the content...
Similar Documents
Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Padmajarani, S. V. Muralidhar, Miryala |
| Copyright Year | 2012 |
| Abstract | binary addition. Parallel Prefix adders are best suited for VLSI implementation. A number of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, logic depth and inter connect count. This paper presents a hybrid high speed and area efficient adder architecture, based on parallel prefix computation by using four operators namely black, gray, O3-black and O3-gray operators. These operators are designed using multiplexers. The proposed hybrid architecture is implemented with 16-bit width operands on Xilinx Spartan 3E FPGA. The experimental results indicate that the proposed architecture is much faster and area efficient. |
| Starting Page | 17 |
| Ending Page | 21 |
| Page Count | 5 |
| File Format | PDF HTM / HTML |
| DOI | 10.5120/9246-3410 |
| Volume Number | 58 |
| Alternate Webpage(s) | http://research.ijcaonline.org/volume58/number1/pxc3883410.pdf |
| Alternate Webpage(s) | https://doi.org/10.5120/9246-3410 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |