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on Chip Design of High-Performance CMOS Imagers , Silicon Retinas , and Image Processing Neural Network Systems with Learning Capability
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wu, Chung-Yu |
| Copyright Year | 2002 |
| Abstract | In the previous research projects, new silicon retina chip, Hopfield neural chips with learning and ratio memory, and neuron-BJT have been successfully developed. In this project, the previous results will be improved and integrated. Moreover, The new compact neuron-bipolar cellular neural network structure with adjustable layer chips for learning and ratio memory will be developed and implemented. These chips together with the necessary interface control chips will be integrated to form a prototyping system for image pattern classification and recognition. It is expected that the system can be applied to the intelligent computer I/O or multi-media systems. A new CMOS imager circuit called the pseudo-active-pixel-sensor (PAPS) structure is proposed and analyzed. It has the advantages of low dark current, high signal-to-noise ratio (S/N), and high fill factor over the conventional passive-pixel sensor (PPS) imager or active-pixel-sensor (APS) image. An experimental chip of new CMOS imager with QCIF (176x144) format is designed. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://ir.nctu.edu.tw/bitstream/11536/96719/2/902215E009113.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
