NDLI: The CMOS design of robust neural chip with the on-chip learning capability

Content Provider	IEEE Xplore Digital Library
Author	Chung-Yu Wu Ron-Yi Liu I-Chang Jou Famm-Jiang Shyh Jye
Copyright Year	1996
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Chung-Yu Wu)
Abstract	A robust neural model-Modified Learning Vector Quantization (MLVQ)-is proposed for the estimation of centroid in pattern recognition. This MLVQ model can significantly demonstrate the behavior of better estimating the class centroid by utilizing the distance-dependent step size. The computer simulation result can indicate the high potential of less dependence on the initial point as well as the precise settlement of the weight vectors to the centroids. The main feature of this model is robust to the noise perturbation to the pattern distributions in practical applications. Also, a mixed-mode of analog-digital processing systems are designed by the CMOS current-mode VLSI technology and paper the best attributes of both analog and digital computation. The final experimental results of this hybrid processing systems can show the on-chip learning capability and operate at microsecond time scale to achieve the goal of real-time neural applications.
Starting Page	426
Ending Page	429
File Size	339101
Page Count	4
File Format	PDF
ISBN	0780330730
DOI	10.1109/ISCAS.1996.541624
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural network hardware Semiconductor device modeling CMOS technology Vector quantization Pattern recognition Computer simulation Noise robustness Application software Analog-digital conversion Process design
Content Type	Text
Resource Type	Article

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