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Automatic Generation of Fault Tolerant VHDL Designs in RTL
| Content Provider | Semantic Scholar |
|---|---|
| Author | Entrena, Luis Lopez, Celia Olías, Emili O |
| Copyright Year | 2001 |
| Abstract | Fault Tolerance (F-T) is an important issue in electronic devices. Detecting and even correcting internal faults during normal operation makes possible the usage of these circuits in critical applications. F-T has been taken into account for many years during design process of these applications, but it has not obtained any profit of latest advances in automatic CAD tools that optimise the design process. Therefore, inserting fault tolerant structures into a circuit has been considered as an external (and heavy) task to the automatic design process. In order to enhance productivity and development time, an automatic CAD tool for helping in the development of fault tolerant circuits is needed. In this paper we propose a new tool for the automatic insertion of fault-tolerant structures in an HDL synthesizable description of the design. With this tool, F-T could be included into any design process with littl e extra cost or development time, by automatically producing a fault tolerant design according user specifications, also described in an HDL, which could be simulated and synthesised with commercial tools. Examples are shown to demonstrate the capabiliti es of this approach. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.uc3m.es/uc3m/dpto/IN/dpin08/FDL_2001.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
