NDLI: Satisfiability based test generation for stuck-at fault coverage in RTL circuits using VHDL

Content Provider	IEEE Xplore Digital Library
Author	Murugesan, S. Ranjithkumar, P.
Copyright Year	2010
Description	Author affiliation: VLSI DESIGN, K. S. Rangasamy college of Technology, Tiruchengode, Namakkal(Dt), India (Murugesan, S.) \|\| Department of ECE, K. S. Rangasamy college of Technology, Tiruchengode, Namakkal(Dt), India (Ranjithkumar, P.)
Abstract	Due to the increasing complexity of modern circuit design, verification has become the major bottleneck of the entire design process. Most efforts are to verify the correctness of the initial Register-Transfer Level (RTL) descriptions written in Hardware Description Language (HDL). A digital system, in general, consists of two main parts: a data path and controller. A validation test set is used to verify controller behaviour and, the controller behaviour exercised by test sequences in a validation test set are reused for detecting faults in the data path. Such controller behaviours are said to be compatible with the corresponding pre-computed test vectors/responses, resulting in the detection of a majority of stuck-at faults in the data path RTL modules. Also, since test generation is performed at the RTL and the controller behaviour is predetermined, test generation time is reduced. The Justification algorithm is used to quickly identify whether the controller behaviour is compatible with pre-computed test pattern and it is a basic factor in affecting the efficiency of algorithms for test generation. Adding Design For Testability (DFT) elements is equivalent to modifying these clauses, such that all the unsatisfiable segment becomes satisfiable. A greedy algorithm is used to select circuit variables for DFT and minimizes the number of DFT elements added to a circuit.
Starting Page	1
Ending Page	6
File Size	168016
Page Count	6
File Format	PDF
ISBN	9781424465910
e-ISBN	9781424465927
DOI	10.1109/ICCCNT.2010.5591856
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-29
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis DFT Discrete Fourier transforms Process control Automatic test pattern generation RTL Circuit faults Integrated circuit modeling Hardware design languages Greedy approach
Content Type	Text
Resource Type	Article

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