Loading...
Please wait, while we are loading the content...
Similar Documents
A Study on Accelerated Built-in Self Test for Error Detecting in Multi-Gbps High Speed Interfaces
| Content Provider | Semantic Scholar |
|---|---|
| Author | Roh, Jun-Wan Kwon, Kee-Won Chun, Jung-Hoon |
| Copyright Year | 2012 |
| Abstract | In this paper, we propose a `linear approximation method` which is an accelerated BER (Bit Error Rate) test method for high speed interfaces, based on an analytical BER model. Both the conventional `Q-factor estimation method` and `linear approximation method` can predict a timing margin for BER with an error of about 0.03UI. This linear approximation method is implemented on a hardware as an accelerated Built-In Self Test (BIST) with an internal BERT (BET Tester). While a direct measurement of a timing margin in a 3Gbps interface takes about 5.6 hours with BER requirement and 95% confidence level, the accelerated BIST estimates a timing margin within 0.6 second without a considerable loss of accuracy. The test results show that the error between the estimated timing margin and the timing margin from an actual measurement using the internal BERT is less than 0.045UI. |
| Starting Page | 226 |
| Ending Page | 233 |
| Page Count | 8 |
| File Format | PDF HTM / HTML |
| DOI | 10.5573/ieek.2012.49.12.226 |
| Volume Number | 49 |
| Alternate Webpage(s) | http://ocean.kisti.re.kr/downfile/volume/ieek/DHJJQ3/2012/v49n12/DHJJQ3_2012_v49n12_226.pdf |
| Alternate Webpage(s) | https://doi.org/10.5573/ieek.2012.49.12.226 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
