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Simulation and Analysis of Different Switch Architectures for Interconnection Networks in MIMD Shared Memory Machines
| Content Provider | Semantic Scholar |
|---|---|
| Author | Dickey, Susan R. Liu, Yuesheng |
| Copyright Year | 2015 |
| Abstract | Differences in switch architectures can have a significant effect on both latency and throughput in interconnection networks, and thus can affect overall performance in shared memory parallel systems with processor to memory interconnection networks. In this paper we describe several switch architectures which differ in the presence or absence of buffers, in the location and functionality of the buffers, and in the width of the data path. Since the addition of an architectural feature may have a significant cost in the complexity or cycle speed of a switching component, it is important to have an accurate assessment of the benefit provided. Therefore, we make quantitative comparisons of switch performance using both simulation and analytical methods. |
| File Format | PDF HTM / HTML |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
