NDLI: A model for parallel simulation of distributed shared memory

Content Provider	IEEE Xplore Digital Library
Author	Barriga, L. Brorsson, M. Ayani, R.
Copyright Year	1996
Description	Author affiliation: Dept. of Teleinf., R. Inst. of Technol., Stockholm, Sweden (Barriga, L.)
Abstract	We present an execution model for parallel simulation of a distributed shared memory architecture. The model captures the processor-memory interaction and abstracts the memory subsystem. Using this model we show how parallel, on-line, partially-ordered memory traces can be correctly predicted without interacting with the memory subsystem. We also outline a parallel optimistic memory simulator that uses these traces, finds a global order among all events, and returns correct data and timing to each processor. A first evaluation of the amount of concurrency that our model can extract for an ideal multiprocessor shows that processors may execute relatively long instruction sequences without violating the causality constraints. However parallel simulation efficiency is highly dependent on the memory consistency model and the application characteristics.
Starting Page	179
Ending Page	184
File Size	651180
Page Count	6
File Format	PDF
ISBN	0818672358
DOI	10.1109/MASCOT.1996.501014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-02-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete event simulation Electronic mail Memory architecture Abstracts Predictive models Timing Data mining Parallel machines Multiprocessor interconnection networks Protocols
Content Type	Text
Resource Type	Article

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