Loading...
Please wait, while we are loading the content...
Similar Documents
Nbti Induced Clock Skew Reduction in Gated Clock Trees
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2014 |
| Abstract | Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show stoppers of circuit reliability in nanometre scale devices due to its deleterious effects on transistor threshold voltage. Interface traps are electrically active physical defects. Interface traps are formed due to crystal mismatches at the Si-Sio2 interface. During oxidation of Si, most of the tetrahedral Si atoms bonds to the formation of weak Si-H bonds, thereby generating interface traps. They are manifested as an increase in absolute PMOS transistor threshold voltage and a reduction in absolute Ion current of PMOS devices making them slower. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits proven to be a growing threat to circuit reliability in nanometer scale technology. The variation in temperature and threshold voltage leads to a phenomenon called NBTI. Clock gating impacts the extent of NBTI induced Vth degradation and, thus increased clock buffers leading to no uniform NBTI degradation and thus increased clock skew. So here we propose a system of the clock gating implementation by selecting NAND or NOR gate as output stage of integrated clock gating cells with the objective of minimizing NBTI induced clock skew. An experimental result shows that, the NBTI induced clock skew is minimized more than up to74%. The main aim is to reduce the delay variation by the clock skew induced due to NBTI and increase the device performance and efficiency. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijsret.org/pdf/120409.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
