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Analysis and optimization of NBTI induced clock skew in gated clock trees (2009)
| Content Provider | CiteSeerX |
|---|---|
| Author | Chakraborty, Ashutosh Ganesan, Gokul Rajaram, Anand Pan, David Z. |
| Description | NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub-100nm VLSI designs. There is little research to quantify its impact on skew of clock trees. This paper demonstrates a mathematical framework to compute the impact of NBTI on gating-enabled clock tree considering their workload depen-dent temperature variation. Circuit design techniques are proposed to deal with NBTI induced clock skew by achieving balance in NBTI degradation of clock devices. Our technique achieves up-to 70 % reduction in clock skew degradation with miniscule (<0.1%) power and area penalty. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2009-01-01 |
| Publisher Institution | In Proceedings of the Design, Automation & Test in Europe |
| Access Restriction | Open |
| Subject Keyword | Sub-100nm Vlsi Design Clock Skew Degradation Workload Depen-dent Temperature Variation Little Research Mathematical Framework Negative Bias Temperature Instability Circuit Design Technique Gated Clock Tree Area Penalty Dominant Pmos Device Failure Mechanism Clock Tree Clock Device Nbti Degradation Gating-enabled Clock Tree Clock Skew |
| Content Type | Text |
| Resource Type | Article |
