Loading...
Please wait, while we are loading the content...
Similar Documents
Solutions for thread interconnection on a NOC CMP
| Content Provider | Semantic Scholar |
|---|---|
| Author | Keslassy, Isaac |
| Copyright Year | 2008 |
| Abstract | Inter-thread communication is expected to be inefficient on network-on-chip based chipmultiprocessors. This is because thread communication is done through memory, and in turn through the cache. This paper reviews solutions for thread communication which are applied to the hardware / software interface. Two solutions create new means of communication between threads that are more appropriate for that purpose than cached memory lines. Another option is allowing the OS to manage the cache, speeding up communication between close threads. A new architecture is suggested which allows the OS to manage the directory entries on CMPs using private-caches. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://eecourses.technion.ac.il/049036/HW-SW%20NOC%20CMP%20Solutions.pdf |
| Alternate Webpage(s) | http://www.ee.technion.ac.il/courses/049036/HW-SW%20NOC%20CMP%20Solutions.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
