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A Processor-Level Framework for High-Performance and High-Dependability
| Content Provider | Semantic Scholar |
|---|---|
| Author | Patel, Sanjay J. Kalbarczyk, Zbigniew T. Iyer, Ravishankar K. Magda, Wojciech G. Nakka, Nithin |
| Copyright Year | 2001 |
| Abstract | This paper presents a processor-level error detection and recovery framework that can operate reliably in the presence of transient errors. In this framework, error detection and recovery modules and programmable hardware (registers, on-chip memory, and control logic) constitute a reliability engine fully integrated with the processor. If the reliability engine detects an error during the processing of a block of code, the architectural state is reverted to the beginning of the block. The paper provides an example of how the proposed framework can boost processor performance while providing higher faulttolerance than a standard processor model. An example of how a processor designed using this framework might be structured is also provided. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.crhc.uiuc.edu/EASY/Papers/patel-easy01.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
