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A processor-level framework for high-performance and high-dependability (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Patel, Sanjay J. Kalbarczyk, Zbigniew Iyer, Ravishankar K. Magda, Wojciech Nakka, Nithin |
| File Format | |
| Language | English |
| Publisher Date | 2001-01-01 |
| Publisher Institution | In Workshop on Evaluating and Architecting Systems for Dependability |
| Access Restriction | Open |
| Subject Keyword | Architectural State Processor-level Error Detection On-chip Memory Recovery Module Recovery Framework Error Detection Processor Performance Reliability Engine Standard Processor Model Programmable Hardware Transient Error Processor-level Framework |
| Content Type | Text |
| Resource Type | Article |