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A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yang, Rong-Jyi Chao, Kuan-Hua Hwu, Sy-Chyuan Liang, Chuan-Kang Liu, Shen-Iuan |
| Copyright Year | 2006 |
| Abstract | A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-/spl mu/m CMOS process and its die area is 1.1/spl times/0.8 mm/sup 2/. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 2/sup 31/-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 2/sup 7/-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10/sup -12/. |
| Starting Page | 1380 |
| Ending Page | 1390 |
| Page Count | 11 |
| File Format | PDF HTM / HTML |
| Volume Number | 41 |
| Alternate Webpage(s) | http://ntur.lib.ntu.edu.tw//bitstream/246246/150239/1/71.pdf |
| Journal | IEEE Journal of Solid-State Circuits |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
