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Code Generation Tools for Hardware Implementation of Fec Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Schuler, Christian |
| Copyright Year | 1992 |
| Abstract | During the last decade the use of hardware description languages (HDL) became an important method for the specification and the design of VLSI circuits. In particular the combination with logic synthesis tools allows a significant acceleration of the design cycle. Further advantages are the use of top down design methodology, reuse of code and retargeting to different semiconductor technologies. Nevertheless there is a lot of effort spend to develop tools and languages, which allow an higher level of abstraction and by this a further improvement of the design efficiency. This paper focuses on application specific code generation tools, which might be used in many areas of digital hardware design. The concept is validated on the example of parameterized Forward Error Correction (FEC) circuits, which are used for error detection or correction in most communication systems. The code generators are able to generate the synthesizable VHDL (Very High Speed Integrated Circuits Hardware Description Language) description of complete FEC encoders and decoders within less than a second. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://home.arcor.de/christianschuler/publ/code_gen.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Automatic programming Code generation (compiler) Digital electronics Encoder Error detection and correction Forward error correction Hardware description language Integrated circuit Logic synthesis Programming Languages Retargeting Reuse (action) Semiconductor Specification Top-down and bottom-up design VHDL VHSIC Very-large-scale integration |
| Content Type | Text |
| Resource Type | Article |
