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A Survey on Floorplan Representations in VLSI
| Content Provider | Semantic Scholar |
|---|---|
| Author | Saha, Soumya Ghosh, Satrajit |
| Copyright Year | 2015 |
| Abstract | In the state of the art of computer designing interconnection of a huge number of circuit elements in a small enough area possess a challenge for the designers. This is possible if the task is divided into smaller independent modules. This is helpful for concurrent design of the individual modules as well. Interestingly the suitable placement and proper interconnection of these modules became an issue in this design. Right placement of the modules is an interesting study that needs to explore the computational aspects of geometrical shapes and appropriate graph theoretical representation. This is helpful for the automation of Floorplan and placement methods and useful in efficient realization of a huge circuit. Efficient representation of Floorplan is an interesting open problem and over few decades many researchers work on this problem to get optimal solution in terms of space and time. This work covers various representational approaches of Floorplan which should be beneficial for junior researchers, wants to start working on this area. Keywords—Floorplan,Sliceable Floorplan, Floorplan Representation, Nonsliceable Floorplan, Mosaic Floorplan, Binary tree, v-h tree, B* tree, O tree, Twin Binary tree. ______________________________________________________________________________________________________________ |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://researchscript.com/wp-content/uploads/2015/04/IJRCS020406.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
