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Ngpe: a New Generalized Polish Expression for Vlsi Floorplan Problem
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2017 |
| Abstract | Floorplanning is one of the most important problems in VLSI circuit design. The main concern is placement of rectangular module s of arbitrary size and shape in such a way that the total area covered by the modules and interconnections should be minimum. It has been found that a floorplan can be classified i nto two categories – Slicing structure and Non Slicing structure. A slicing structure floorpla n can be obtained by repetitively cutting the floorplan horizontally or vertically, where as Non slicing structure floorplan cannot. A binary tree can be used to represent a slicing floo rp an on the basis of the slicing property. The advantages of slicing representation are genera lly found smaller encoding cost and solution space for faster runtime for packing. Besi d , it is flexible to deal with hard, preplaced, soft and rectangular blocks. But the sol ution space of slicing structure may not be the optimal solution. On the other hand, in Non slicing structure the optimal solution might be achieved but it needs more evaluating runt ime for packing than slicing approach. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://shodhganga.inflibnet.ac.in/bitstream/10603/193061/11/11_chapter%205.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
