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SYSTEM-ON-A-CHIPSTRUCTURE HAVING A MULTIPLE CHANNEL BUS BRIDGE BACKGROUND OF THE INVENTION 1. Field of the Invention
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2017 |
| Abstract | (22) Filed: Nov. 9, 2000 A System-on-a-chip integrated circuit Structure includes a 9 bridge having a plurality of channels, a processor local bus (51) Int. Cl. connected to the bridge (wherein the bridge includes a first G06F 13/14 (2006.01) channel dedicated to the processor local bus), at least one (52) U.S. CI. 710/305; 710/306 logic device connected to the processor local bus, a periph (58) Field of Classification search. 710/100 eral device bus connected to the bridge (wherein the bridge 710/306, 305 240344. 4 f1.430 includes a Second channel dedicated to the peripheral device See application file for complete Search history bus), at least one peripheral device connected to the periph eral device bus, at least one memory unit connected to the (56) References Cited bridge (wherein the bridge includes a third channel dedi cated to the memory unit), and at least one input/output unit U.S. PATENT DOCUMENTS connected to the bridge (wherein the bridge includes a fourth 5438.681 A 8/1995 Mensch, Jr. channel dedicated to the input/output unit). 5,455,525 A 10/1995 Ho et al. 5,761,516 A 6/1998 Rostoker et al. 27 Claims, 4 Drawing Sheets |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://patentimages.storage.googleapis.com/7a/10/e8/cc2609dc7dd387/US6985988.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
