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Design and Implementation of on-board satellite encryption with SEU error detection & correction code on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mohamed, Samah Shehata, Khaled A. Ali Issa, Hanady H. Shaker, Nabil Hamdy |
| Copyright Year | 2016 |
| Abstract | Earth Observation (EO) satellites in Low Earth Orbit (LEO) provide earth with data required for both military and civilian applications. Satellite manufactures are realizing that security is essential issue in satellite communications. Advanced Encryption Standard (AES) is one of the important candidates to secure satellite communications. Harsh radiation is the main feature of LEO environment which causes Single Event Upsets (SEUs). On-board encryption processor needs to be robust enough for faults in order to avoid transmission of erroneous data to ground. The presented algorithm in this paper combines AES with Hamming error detection and correction code to protect the on-board encryption process from SEU. The proposed fault tolerant algorithm is designed using the Hardware Description Language (HDL) design entry and implemented on Xilinx Field Programmable Gate Arrays (FPGAs) virtex6. KeywordsAES, SEU, Hamming Error Detection and Correction Code, VHDL, FPGA. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://worldcomp-proceedings.com/proc/p2016/SAM9723.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
