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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Li Hao Lixin Yu |
| Copyright Year | 2008 |
| Description | Author affiliation: Beijing Microelectron. Technol. Inst., Beijing (Li Hao; Lixin Yu) |
| Abstract | This article proposes a method which reduces delay and area in EDAC circuits. A SEC-DED Hsiao code (39,32) and a DEC systematic (1 6, 8) code used for the hardware implementation of EDAC, are discussed and compared. Two codes are all proposed by the authors in earlier paper. In terms of parity-check matrix of these codes, this article presents a low-cost generation method of check bits. Simulation results show the delay and area of check bits generator based on 2-input XOR gates structure in the smic 180 nm process case. EDAC for 32 bits data, SEC-DED Hsiao code(32,7) need less extra memory bits than DEC systematic (1 6, 8) code ,but SEC-DED Hsiao code(32,7) take more delay and area , Which show that different code and different implementation can affect the cost of EDAC circuitry and be used as a guide for selecting the proper Code for different application requirements. |
| Starting Page | 222 |
| Ending Page | 225 |
| File Size | 307180 |
| Page Count | 4 |
| File Format | |
| ISBN | 9780769534077 |
| DOI | 10.1109/ICCIT.2008.14 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-11-11 |
| Publisher Place | South Korea |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Single event upset Circuits Electrical fault detection memory fault tolerance double error correction (DEC) code Delay hardware-implemention Fault detection Error detection and correction (EDAC) single error upset (SEU) Hardware Parity check codes Error correction Error correction codes Single error correction and double error detection (SEC-DED) code |
| Content Type | Text |
| Resource Type | Article |
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