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A next-gen FPGA-based SoC verification platform
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mao, Howard |
| Copyright Year | 2019 |
| Abstract | System-on-Chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market pressures. All of this is putting tremendous demands on SoC design and verification teams. Indeed, it is now widely accepted that verification accounts for around 70 percent of the total SoC development cycle. Thus, anything that decreases verification costs, speeds verification runs, and allows verification to be deployed earlier in the development cycle is of extreme interest. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.edn.com/Pdf/ViewPdf?contentItemId=4210294 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |