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Design of a current Mode Sample and Hold Circuit at sampling rate of 150 MS/s
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yadav, Prity Saini, Anu |
| Copyright Year | 2014 |
| Abstract | A current mode sample and hold circuit is presented in this paper at 180nm technology. The major concerns of VLSI are area, power, delay and speed. Hence, we have used a MOSFET in triode region in the proposed architecture for voltage to current conversion instead of a resistor being used in previously proposed circuit. The proposed circuit achieves high sampling frequency and with more accuracy than the previous one. The performance of the proposed circuit is depicted in the form of simulation results. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijera.com/papers/Vol4_issue10/Part%20-%203/R41003120122.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
