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A 1.5v,100ms/s,12-bit current-mode cmos sample-and-hold circuit.
| Content Provider | CiteSeerX |
|---|---|
| Author | Hashemipour, O. Nabavi, S. G. |
| Abstract | Abstract—A high-linearity and high-speed current-mode sampleand-hold circuit is designed and simulated using a 0.25μm CMOS technology. This circuit design is based on low voltage and it utilizes a fully differential circuit. Due to the use of only two switches the switch related noise has been reduced. Signal- dependent-error is completely eliminated by a new zero voltage switching technique. The circuit has a linearity error equal to ±0.05μa, i.e. 12-bit accuracy with a ±160 μa differential output- input signal frequency of 5MHZ, and sampling frequency of 100 MHZ. Third harmonic is equal to –78dB. |
| File Format | |
| Access Restriction | Open |
| Content Type | Text |