NDLI: Register Pressure Aware Code Selection Algorithm for Multi-Output Instructions

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Register Pressure Aware Code Selection Algorithm for Multi-Output Instructions

Content Provider	Semantic Scholar
Author	Youn, Jonghee M. Paek, Yunheung Ko, Kwang-Man
Copyright Year	2012
Abstract	The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a - (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.
Starting Page	45
Ending Page	50
Page Count	6
File Format	PDF HTM / HTML
DOI	10.3745/KIPSTA.2012.19A.1.045
Alternate Webpage(s)	http://ocean.kisti.re.kr/downfile/volume/kips/JBCREI/2012/v19An1/JBCREI_2012_v19An1_45.pdf
Alternate Webpage(s)	https://doi.org/10.3745/KIPSTA.2012.19A.1.045
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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