NDLI: Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions

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Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions

Content Provider	ACM Digital Library
Author	Böhm, Igor Franke, Björn Edler von Koch, Tobias J.K.
Abstract	For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM Thumb, where the processor either operates in standard or compact instruction mode. The ARCompact ISA considered in this paper is different in that it allows freeform mixing of 16- and 32-bit instructions without a mode switch. Compact 16-bit instructions can be used anywhere in the code given that additional register constraints are satisfied. In this paper we present an integrated instruction selection and register allocation methodology and develop two approaches for mixed-mode code generation: a simple opportunistic scheme and a more advanced feedback-guided instruction selection scheme. We have implemented a code generator targeting the ARCompact ISA and evaluated its effectiveness against the ARC750D embedded processor and the EEMBC benchmark suite. On average, we achieve a code size reduction of 16.7% across all benchmarks whilst at the same time improving performance by on average 17.7%.
Starting Page	180
Ending Page	189
Page Count	10
File Format	PDF
ISBN	9781605586359
DOI	10.1145/1772954.1772980
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-04-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Variable-length instructions Code size Dual instruction set architecture Instruction selection Register allocation Arcompact
Content Type	Text
Resource Type	Article

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Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.

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