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DesignCon 2013 Power Supply Noise Induced Jitter Estimation in High Speed Clock Tree for Full Chip Timing Analysis
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2013 |
| Abstract | As semiconductor technology advances, low supply voltage and high performance requirements make the clock jitter more critical to the integrated circuit (IC) design. In this paper, a 32nm test vehicle is built to characterize and analyze on-chip power supply noise. Clock jitter sensitivity to noise frequency and amplitude is investigated. By studying noise characteristics and jitter sensitivity to noise, a cell based jitter model generation method is introduced. This enables clock tree jitter calculation and flexible “what if” analysis with reduced run time, which is the key for STA early on in the design phase. The estimation result on a real design is studied and shows good correlation to conventional jitter analysis method. Author(s) Biography Wen Yin is technical leader of packaging engineering solutions and signal integrity analysis from ASIC design center at IBM China Corporation. His current focus includes 3DIC solutions, packaging engineering, and power integrity/signal integrity in ASICs used in high speed network systems. He received BS degree in electronics engineering from Huazhong Science and Technology University, and MS degree in Microelectronics from Shanghai Jiao Tong University. Ze Gui Pang is hardware engineer from IBM China ASIC design center. He focus on package design and power noise analysis, supporting high speed ASIC package solutions, design automation, on-chip power noise analysis and high speed SerDes interface modeling. He received BS and MS degree of microelectronics from Xi Dian University. Wei Liu is hardware engineer from IBM China. She focus on package design, power integrity/signal integrity in ASICs used in high speed network system, supporting design automation, on-chip power noise analysis. She received BS and MS degree of microelectronics from Fu Dan University. Tong Hao Ding is staff hardware engineer from IBM China ASIC design center. He focus on package design, power integrity/signal integrity in high speed circuit system design. He received the B.S. degree in electrical engineering from Xidian University, China, in 2007, and Ph.D degree in electrical engineering from Xidian University, China, in 2012. Erik Breiland has been an application engineer from IBM Burlington for the last 7 years of his 14 years with IBM. Prior work included noise tool development, HSS package design, and SSO model to hardware correlation. His current focus is on-chip power integrity, I/O noise analysis, and resonance analysis of customer ASIC Designs. He is also helping develop the noise tool automation and support of current tools and methodology. He received his BS in Electrical Engineering from the Rensselaer Polytechnic Institute in 1998, and an MS in Electrical Engineering in 2005 from the University of Vermont. Introduction As semiconductor technology advances and IC frequency goes higher with lower voltage, clock period jitter acts more and more important role in chip design. Jitter directly reduces timing window between capture and launch sequential elements [1]. Conventional jitter analysis method to estimate clock tree jitter is shown in Figure 1. Figure 1. Conventional jitter analysis method The HSPICE netlist of the clock path is built with cell spice model and extracted interconnect parasitic RC model. The power supply with transient noise for each cell is extracted from whole chip power supply noise analysis tool. Piece Wise Linear (PWL) waveform from analysis tool for each cell is set to cell supply pin (Vdd0, Vdd1 . Vddn) to enable HSPICE simulation. Jitter is measured at the output of the clock sink. This method deployment is limited by the simulation run time, which is up to weeks for a typical clock tree. Therefore this method can be used for a few of specific critical clock path analysis but not suitable to perform chip scale analysis, and it is not able to meet fast design turnaround time and quick “what if” analysis. In this paper, a fast jitter estimation method is proposed. This method can be run early in the chip's floorplan stage when clock buffers are placed. The estimation results can be back annotated to Static Timing Analysis (STA) tool, in order to assess full chip timing degradation due to clock jitter at early design phase. Corrective actions can be taken to mitigate clock jitter according to jitter analysis. It helps avoid no-timing-window issue in later design. In this method, the key is cell based jitter model generation for clock tree jitter calculation. It is based upon understanding of on-chip power supply noise characteristics, and clock buffer cell jitter sensitivity to noise frequency and amplitude. Runtime is significantly reduced by using the fast jitter estimation method and analysis results accuracy is acceptable because experimental run shows good correlation to conventional jitter analysis method. Understanding On-Chip Power Supply Noise Figure 2 shows a typical power supply noise measured at the circuit point of a 32nm test chip, running continuous switching test pattern after certain delay from the beginning. Figure 2. At-circuit power supply characteristics In Figure 2, at-circuit power supply experiences abrupt drop, followed by voltage bounce due to off-chip recharge and finally settle down with periodic variation riding on a stable voltage. Step response occurs when chip power demand changes abruptly and the inductance of Power Distribution Network (PDN) limits current delivery from power supply. The minimum voltage of step response is determined by the characteristics of PDN and the time and magnitude of power change. The damped oscillation of step response indicates how PDN response to a power demand change which also reveals the characteristic of the PDN such as resonant frequency, which is typically tens to hundreds MHz level. Steady-State AC response is induced by high frequency switching of on chip circuits and primarily a function of chip quiet capacitance and the switch current drained by these circuits [2]. Static IR drop is the average voltage after power supply reaches steady state. It is a function of average power and resistance of PDN. Power supply noise can be thought of as the summation of multiple sinusoids with decaying amplitudes. When step response dies out, the resonant frequency dominates and the supply voltage distribution approaches that of a sinusoid [3]. For very large scale chip in 32nm technology or beyond, the internal circuit is switching at a much higher frequency than the resonance of the PDN. Power supply could not response quickly enough to mitigate the voltage drop, and the transient noise due to PDN resonance acts like DC supply for circuits switching at high frequency. The circuit delay varies to the supply voltage, which induces timing uncertainty. The growth of chip integration and complexity drives the increase of the die size. The clock tree spreads out, suffering more power supply noise from each noise aggressor in different areas. As shown in Figure 3, the power supply noise distribution across the chip has different power supply noise magnitude due to specific floorplan density and circuits' current demand. This non uniform noise distribution causes more complexity in predicting the clock jitter [4-6]. Figure 3. Power supply noise distribution Jitter Sensitivity to Noise Frequency Based on the period jitter definition [7], the square of the root mean square (RMS) period jitter can be derived as 2 2 1 2 0 RMS n n J E R R (1) where n is phase jitter of the nth period; R is autocorrelation function of the phase noise n with time interval . The autocorrelation function R could also be represent with power spectral density J S j as |
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| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
