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A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal
| Content Provider | Semantic Scholar |
|---|---|
| Author | Lee, Tsung-Sum Lu, Chi-Chang |
| Copyright Year | 2005 |
| Abstract | A new technique for realizing a high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The design consideration of the building blocks is described in detailed. A prototype circuit in a 0.5-μ m CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 200 MHz of sampling frequency with less than −56.5 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8Vpp. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.6 ns acquisition time at 0.8 V step input, and 0.8 Vpp full-scale differential input range are achieved. The circuit dissipates 4.8 mW with a ± 1.5 V power supply. |
| Starting Page | 37 |
| Ending Page | 46 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.1007/s10470-005-3422-z |
| Alternate Webpage(s) | https://page-one.springer.com/pdf/preview/10.1007/s10470-005-3422-z |
| Alternate Webpage(s) | https://doi.org/10.1007/s10470-005-3422-z |
| Volume Number | 45 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
