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Low-Power Standard Cell Library for Synthesis
| Content Provider | Semantic Scholar |
|---|---|
| Author | Hirsch, Romy |
| Copyright Year | 1998 |
| Abstract | The realization of deep sub-micron technologies and the increase in the density of Integrated Circuits (ICs) have made power consumption a major concem in VLSI design. Advanced IC design rnethodologies employ automatic synthesis tools in conjunction with standard celi libraries to implement digital circuits. h this thesis, a low power celI library is developed, with the objective of minimiMg the power dissipation of spthesized circuits. The thesis contains an analysis of the power and speed char2ctenstics of different size cek , and presents a technique that allows to nade speed for power without comprornising performance requirements. An experimental infrastructure which determines the power consumption of relatively large circuits has been created to evaluate the quality of the Iibrary. Three benchmark designs are used to illustrate the performance of several versions of the library (in tems of power dissipation), and simulation results predict up to a 30% improvement in the power consumption of designs mapped to the proposed library. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.nlc-bnc.ca/obj/s4/f2/dsk2/tape17/PQDD_0026/MQ26983.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Benchmark (computing) Digital electronics Integrated circuit design Libraries Requirement Simulation Standard cell Version Very-large-scale integration |
| Content Type | Text |
| Resource Type | Article |
