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Vhdl-translation for Bdd-based Formal Veriication
| Content Provider | Semantic Scholar |
|---|---|
| Author | Payer, Michael Venzl, Gerd |
| Copyright Year | 1994 |
| Abstract | We describe a novel approach to translate a reasonably large subset of VHDL into BDD's. The VDHL subset was chosen to include the commonly used synthesis subsets but is strictly based on the simulation semantics required by [2]. Our results signi cantly improve on the previously reported ones [5]. We also investigate the inherent complexity of dealing with the VHDL semantics as opposed to translating netlists into BDDbased FSM's. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.pldworld.com/_hdl/1/VHDL_Internet/papers/vhdl2fsm.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
