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Formal Veriication of Safety Properties in Timed Circuits Formal Veriication of Safety Properties in Timed Circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Cortadellaz, Jordi Kondratyev, Alex Pastoryy, Enric |
| Copyright Year | 1999 |
| Abstract | The incorporation of timing makes system veriication computationally expensive. This paper proposes a new approach for the veriication of timed circuits. Rather than calculating the exact timed state space, a conservative overestimation that fulllls the property under veriication is derived. Timing analysis with absolute delays is eeciently performed at the level of event structures and transformed into a set relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be eeciently combined with timing analysis. Moreover, the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than 10 5 untimed states can be veriied. |
| File Format | PDF HTM / HTML |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
