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Efficient folded VLSI architectures for linear prediction error filters

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BMU PMU TBU SMU Efficient Architecture for Error Control Coding Using VLSI

Low complexity, low power vlsi architectures for image codecs

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Low-power VLSI decoder architectures for LDPC codes

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Energy-aware error control coding for Flash memories

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Algorithms and VLSI architectures for low-power mobile face verification

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Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures

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Low power coding approach with error free coding scheme in vlsi design 1.