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Proposal and Design of SALTran: A New Surface Accumulation Layer Transistor for Enhanced Current Gain
| Content Provider | Semantic Scholar |
|---|---|
| Author | Parihar, Vinod |
| Copyright Year | 2004 |
| Abstract | Whether for driving highly capacitive loads using BiCMOS technology or in high voltage applications and in many mixed signal and precision analog applications, bipolar transistors are inevitable. To combine the high-density integration of MOS logic with the current-driving capabilities of BJT along with better device isolation of Silicon-on-Insulator (SOI), BiCMOS technology has opened up new avenues for the lateral bipolar transistors (LBT) on SOI. To meet the strict demand on device performance parameters such as β, gm and fT, many structures like HBTs and polysilicon BJTs are already in use. But these require complex process steps and also suffer from collector emitter offset voltage in the case of HBTs and high emitter resistance in the case of polysilicon emitter transistors. Surface Accumulation Layer Transistor (SALTran) is proposed for the first time to offer an alternative way of meeting the stringent performance parameters requirements, by just changing the emitter contact and emitter doping in conventional bipolar transistors. Using process and device simulations, we have demonstrated the SALTran concept both on NPN and PNP LBT on SOI structures to obtain high performance in terms of high current gain, better thermal stability, and less hot carrier degradation without significantly affecting the cut-off frequency. We have also implemented the SALTran concept on power SiC BJT and showed through our simulations the superiority of the power SALTran. Our simulations show that the SALTran concept is useful to both lateral and vertical bipolar transistors whether they are high speed or high voltage structures. In conclusion, we have demonstrated the superior attributes offered by the SALTran structure, supported by extensive simulation studies. The proposed structures should be very useful for VLSI and power applications. The results presented in this work are expected to provide incentive for further experimental applications. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://web.iitd.ac.in/~mamidala/HTMLobj-205/thesis_final.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Thesis |
