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Registers Size Innuence on Vector Architectures
| Content Provider | Semantic Scholar |
|---|---|
| Author | Espasa, Roger Valero, Mateo |
| Copyright Year | 2007 |
| Abstract | In this work we have studied the innuence of the vector register size over two diierent concepts of vector architectures. We have observed that, long vector registers play an important role in a conventional vector architecture. However, we observed that even using highly vectorizable codes, only a small fraction of that large vector registers is used. Nevertheless, we have observed that, reducing vector register size on a conventional vector architecture, result in a severe performance degradation , providing slowdowns in the range of 1.8 to 3.8. When we including an out-of-order execution on a vector architecture, the necessity of long vector registers, is reduced. We have used a trace driven approach to simulate a selection of the Perfect Club and Specfp92 programs. The results of the simulations show that, the register size reduction on an out-of-order vector architecture is less negative than in a conventional vector machine, providing slowdowns in the range of 1.04 to 1.9. Even when reducing the registers size to 1/4 the original size on an out-of-order machine , the slowdown provided is in the range of 1.04 to 1.5, but it still is better than a conventional vector machine. Finally, when comparing both architectures, using the same register le size, (8kb), we can see that the performance gained by using out-of-order execution is in the range of 1.13 to 1.40. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ac.upc.es/homes/luisv/papers/VECPAR98.ps.Z |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
