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Effective Usage of Vector Registers in Decoupled Vector Architectures (1997)
| Content Provider | CiteSeerX |
|---|---|
| Author | Villa, Luis Espasa, Roger Valero, Mateo |
| Description | This paper presents a study of the impact of reducing the vector register size in a decoupled vector architecture. In traditional in-order vector architectures, long vector registers have typically been the norm. We start presenting data that shows that, even for highly vectorizable codes, only a small fraction of all elements of a long vector register are actually used. We also show that reducing the register size in a traditional vector architecture in an attempt to reduce hardware cost and maximize register utilization results in a severe performance degradation. However, we combine the decoupling technique with the vector register reduction and show that the resulting architecture tolerates very well the register size cuts. We simulate a selection of Perfect Club and Specfp92 programs using a trace driven approach and compare the execution time in a conventional vector architecture with a decoupled vector architecture using different registers sizes. Halving the register size and u... In Parallel and Distributed Processing (PDP98 |
| File Format | |
| Language | English |
| Publisher Date | 1997-01-01 |
| Access Restriction | Open |
| Subject Keyword | Perfect Club Vector Register Size Vector Register Reduction Execution Time Hardware Cost Vectorizable Code Severe Performance Degradation Effective Usage Register Size Traditional In-order Vector Architecture Vector Register Conventional Vector Architecture Register Size Cut Traditional Vector Architecture Long Vector Register Different Register Size Specfp92 Program Small Fraction Utilization Result Decoupled Vector Architecture Resulting Architecture Decoupling Technique |
| Content Type | Text |
| Resource Type | Article |
