NDLI: DesignCon 2008 On-Chip Instrumentation for In-System IP Validation of a 6 Gbps Serial ATA Platform Device

Please wait, while we are loading the content...

DesignCon 2008 On-Chip Instrumentation for In-System IP Validation of a 6 Gbps Serial ATA Platform Device

Content Provider	Semantic Scholar
Author	Schrader, Martin
Copyright Year	2007
Abstract	This paper describes an innovative solution to the challenges of in-system IP validation, in particular the implementation and silicon results for a new, high-speed, 6 Gigabit-per-second Serial-ATA platform chip from Infineon. Using a commercially available silicon validation platform, Infineon successfully inserted the on-chip instrumentation with the newly developed Infineon IP, and employed it in silicon, to both validate and optimize the 90nm platform device for use by Infineon's licensees. Additional results describe downstream system-level development and analysis applications, enabled through the use of an API to access the on-chip instrumentation in the lab to monitor communications between the IP blocks. Martin Schrader is Staff Engineer Digital Design and Project Manager, ASIC Design and Security (ADS) Business Unit at Infineon Technologies. He is responsible for SATA IP core development and integration into customer SoC. He founded the Serial Interfaces Expert Group of Infineon ADS and is member of the digital workgroup of the SATA International Organization (SATA IO). Martin has over 9 years of experience in digital design and project management working with worldwide cross functional teams. Daniel Hoggar is Director of Applications Engineering at DAFCA. He has extensive experience in EDA and ASIC Design most notably in areas of physical synthesis and optimization. Prior to DAFCA, Daniel leveraged his technical expertise as the Product Specialist at TeraSystems. He has also held multiple technical positions during seven years with Mentor Graphics and before that,
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://www.dafca.com/downloads/DesignCon2008_DAFCA_Infineon_Paper.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in