Loading...
Please wait, while we are loading the content...
Similar Documents
Implementation and Evaluation of Register Tiling for Perfectly Nested Loops
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rajaraman, Bhargavi |
| Copyright Year | 2009 |
| Abstract | Tiling is a crucial loop transformation for generating high-performance code on modern architectures to expose coarse grain parallelism in multi-core architectures and to maximize data reuse in deep memory hierarchies. Register tiling improves Instruction Level Parallelism and is critical for these architectures to maximize performance improvements. Tiled loops with parameterized tile sizes facilitate runtime feedback used in iterative compilation and empirical tuning. Chunky Loop Generator (CLooG) is a powerful polyhedral code generator used to generate syntactic code from polyhedral representation of statement domains and data dependences. However, optimizations like loop unrolling and register tiling can only be applied syntactically. We implement register tiling algorithm for perfectly nested loops for rectangular and non rectangular iteration spaces by post processing CLooG ASTs. There are numerous tools like Pluto, TLoG and HiTLoG that use CLooG to generate code after finding various optimizations through polyhedral approaches. An implementation of register tiling in CLooG can give higher performance improvements for generated code. Experimental results using a number of computational benchmarks comparing tiling techniques implemented in CLooG and TLoG, demonstrate the effectiveness of the implemented tiling algorithm. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://etd.ohiolink.edu/!etd.send_file?accession=osu1245123518&disposition=inline |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
