NDLI: Parametric multi-level tiling of imperfectly nested loops

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Parametric multi-level tiling of imperfectly nested loops

Content Provider	ACM Digital Library
Author	Krishnamoorthy, Sriram Ramanujam, J. Hartono, Albert Norris, Boyana Baskaran, Muthu Manikandan Bastoul, Cédric Cohen, Albert Sadayappan, P.
Abstract	Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multi-level tiled code is essential for maximizing data reuse in systems with deep memory hierarchies. Tiled loops with parametric tile sizes (not compile-time constants) facilitate runtime feedback and dynamic optimizations used in iterative compilation and automatic tuning. Previous parametric multi-level tiling approaches have been restricted to perfectly nested loops, where all assignment statements are contained inside the innermost loop of a loop nest. Previous solutions to tiling for imperfect loop nests have only handled fixed tile sizes. In this paper, we present an approach to parametric multi-level tiling of imperfectly nested loops. The tiling technique generates loops that iterate over full rectangular tiles, making them amenable to compiler optimizations such as register tiling. Experimental results using a number of computational benchmarks demonstrate the effectiveness of the developed tiling approach.
Starting Page	147
Ending Page	157
Page Count	11
File Format	PDF
ISBN	9781605584980
DOI	10.1145/1542275.1542301
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Imperfectly nested loops Parametric tiling
Content Type	Text
Resource Type	Article

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