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Master-slave Flip-flop with Low Power Consumption Cross-reference to Related Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Cheng, Zhihong Nguyen, Long H. |
| Copyright Year | 2017 |
| Abstract | In a master-slave flip-flop, the master latch has first and sec ond three-state stages, and a first feedback stage. The slave latch has third and fourth three-state stages, and a second feedback stage. First and second clock Switches having oppo site phases are provided. The first clock Switch is configured in one of the first and fourth three-state stages, and the other stage shares the first clock Switch. The second clock Switch is configured in one of the second and third three-state stages, and the other stage shares the second clock Switch. The sec ond three-state stage has an additional pair of complementary devices having signal paths connected in series with each other with both being gated by a data output of the slave latch. The flip-flop reduces the number of clock switches and clock Switch power consumption. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://patentimages.storage.googleapis.com/83/a8/7e/55c4536e6e35f1/US8941429.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Patent |
