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Vhdl Modeling, Test, and Distribution 2 Vhdl Modeling at Msu 2.1 Modeling Overview
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sanders, V. Reese, Robert B. Knight, Aubrey K. Calhoun, J. Scott |
| Copyright Year | 1998 |
| Abstract | This paper presents the ongoing effort of the Mississippi State University / Microsystems Prototyping Laboratory (MSU/MPL) executed as part of the RASSP Technology Base Program. The research underway includes: VHDL model development, VHDL test bench synthesis, and utilization of the World Wide Web (WWW) to document and distribute models, tools, and information. To date, modeling guide lines have been implemented for PROMs, SRAMs, Dual–Port SRAMs, FIFOs, and PLDs. Successful models have been developed using these guidelines. Guidelines for CPLDs and FPGAs are currently being developed. A VHDL Test Bench Synthesis Tool has been developed and is scheduled for beta testing in July 1995. This tool automatically generates VHDL test benches and allows for vendor independent testing methodologies of VHDL designs. The World Wide Web (WWW) is being used to document and release the VHDL models developed. Complete datasheets for sample models have been developed and posted to the Web as an example of hierarchical electronic datasheets. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.pldworld.com/_hdl/1/VHDL_Internet/papers/vhdl-mtd.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
