Loading...
Please wait, while we are loading the content...
Similar Documents
An Overview of the Thesis Chapter 2 Cache Review and Modeling Power Consumption 2.1 Cache Review 2.1.1 Review of Cache Organization
| Content Provider | Semantic Scholar |
|---|---|
| Abstract | Introduction Nowadays, portable devices such as laptop and notebook computers are very popular. These devices require energy efficient design in order to maximize battery lifetime. Reducing the power consumption of microprocessors has become increasingly important. Many studies have shown that memory accesses account for a noticeably large percentage of the total power consumption in microprocessors, making the power consumption of caches and main memory an important concern [13]. Caches are a significant part of the processor due to the increasing disparity between processor cycle time and memory access time. High performance microprocessors normally have one or two levels of on-chip cache in order to reduce the off-chip traffic as much as possible. Off-chip accesses are not only at least a magnitude slower but also dissipate a large amount of power via highly capacitive I/O pads. Thus, caches are important not only for high performance, but also for low power to help reduce the amount of off-chip communication. The power dissipated by the on-chip cache itself is often a significant part of the power dissipated by the entire microprocessor. For example, in the StrongARM 110 from DEC and the Power PC from IBM, cache power consumption is either the largest or second largest power-consuming block [13]. In the StrongARM CPU which has the current best SPECmarks/ watt rating, 43% of total power is dissipated in the on-chip caches [11]. Another example is the 2 DEC 21164 microprocessor, whose on-chip cache dissipates 25% of the total power [11]. Hence, to achieve an energy efficient design, it is necessary to reduce the power dissipation in the on-chip caches. In a typical processor with a split cache architecture, the instruction cache (I-cache) consumes more power than the data cache (D-cache) because the I-cache is accessed for each instruction while the D-cache is accessed only for loads and stores. Since around 25-30% of the executed instructions are loads and stores, the activity of the D-cache is around 25-30% of the activity of the I-cache. Clearly, the I-cache is an attractive target to reduce power consumption. This thesis, therefore, focuses on reducing the power consumption of the level-1 I-cache by using an in-cache instruction compression technique that uses gated wordlines to reduce the number of bits read for compressed instructions. To accurately estimate cache power, we have developed a cache power consumption model as well as a cache simulator. The analytical model for estimating cache power … |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://groups.csail.mit.edu/cag/scale/papers/pmukaya/thesis_version1.pdf |
| Alternate Webpage(s) | http://www.cag.csail.mit.edu/scale/papers/pmukaya/thesis_version1.pdf |
| Alternate Webpage(s) | http://www.cag.lcs.mit.edu/scale/papers/pmukaya/thesis_version1.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
